Discrete Trap Memories (DTM) contribute substantially to the development of Flash memory. FIG. 1 is a schematic drawing of DTM 100. Source 101 and drain 102 are formed in substrate 103, which is typically a silicon layer. Bottom oxide layer 104 is thermally grown on silicon 103. Nitride layer 105 is deposited on bottom oxide layer 104 and holds discrete charge traps 106. Top oxide layer 107 is grown or deposited on nitride layer 105. Gate layer 108, which may be polycrystalline silicon or metal, is deposited on top oxide layer 107. This structure is well known and is referred to as SONOS or MONOS. The local potential of the channel, and therefore the local threshold voltage, will be modified by charging of the discrete charge traps 106 with electrons. The DTM device 100 operates such that when a voltage higher than the threshold voltage is applied to gate 108, a percolation path between source 101 and drain 102 allows current to flow through the device. The course of the percolation path depends upon the distribution of traps 106 as described, for example, in D. Ielmini et al., A new channel percolation model for VT shift in discrete-trap memories, Reliability Physics Symposium Proceedings, 42nd Annual 2004, 515-521 (25-29 Apr. 2004 IEEE International), the disclosure of which is hereby incorporated by reference herein in its entirety.